Packet Buffer DMA

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AXI memory space.

The controller uses a packet buffer with the following advantages.

64 data bus width support.

Achieve the maximum line rate by storing multiple frames in the packet buffer.

Efficient use of the AXI interface.

Full store and forward.

Support for transmit TCP/IP checksum offload.

Support for priority queuing.

When a collision on the line occurs during transmission, the packet is automatically replayed directly from the packet buffer memory rather than having to re-fetch through the AXI interface.

Received error packets are automatically dropped before any of the packet is presented to the AXI, reducing AXI activity.

Supports manual RX packet flush capabilities.

Optional RX packet flush when there is lack of AXI resources.