Page Read Command

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The generic FIFO contents for the read command are listed in Table: Generic FIFO Contents for Read Command.

Table 24-21:      Generic FIFO Contents for Read Command

Description

Reserved

Poll

Stripe

Receive

Transmit

Data Bus Select

CS_
Upper

CS_
Lower

SPI Mode

Exponent

Data
_xfer

Immediate
_Data

 

31:20

19

18

17

16

15:14

13

12

11:10

9

8

7:0

Start driving chip select (CS). Setup time is four QSPI_REF_CLK cycles.

12'd0

1'b0

1'b0

1'b0

1'b0

2'b01

1'b0

1'b1

2'b01

1'b0

1'b0

8'h04

Send opcode 03 for page read. Start driving chip select and clock.

12'd0

1'b0

1'b0

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

1'b0

8'h03

Send first address byte 10.

12'd0

1'b0

1'b0

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

1'b0

8'h10

Send second address byte 20.

12'd0

1'b0

1'b0

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

1'b0

8'h20

Send third address byte 30.

12'd0

1'b0

1'b0

1'b0

1'b1

2'b01

1'b0

1'b1

2'b01

1'b0

1'b0

8'h30

Read 100 bytes.

12'd0

1'b0

1'b0

1'b1

1'b0

2'b01

1'b0

1'b1

2'b01

1'b0

1'b1

8'h64

Stop CS/SCLK, chip-select is deasserted. CS hold time is three reference clock cycles (optional).

12'd0

1'b0

1'b0

1'b0

1'b0

2'b01

1'b0

1'b0

2'b01

1'b0

1'b0

8'h04