Phase Interpolator

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PI receives the 0° and 180° phases of the half-rate CMOS-level clocks from the clock processor. The PI provides four quadrature phases of the CML-level half-rate clock that are phase shifted as compared to the input clocks as dictated by the PI code coming from the clock and data recovery loop filter (CDRLF). The PI can shift the recovered clocks with a resolution of UI/32. The samplers use these clocks to sample the receive data over a span of two UI. Table: CMOS-level Clocks describes these clocks. Each clock is 90° out of phase with the next clock.

Table 29-5:      CMOS-level Clocks

Clock

Clock Usage

I clock

Samples the data in the middle of the first data eye.

Q clock

Samples the data at the edge between the first and second data eyes.

I-bar clock

Samples the data in the middle of the second data eye.

Q-bar clock

Samples the data at the edge at the end of the second data eye.

The CDRLF uses the feedback path to control the PI where the phase of the clocks are lined up where they are expected to be, relative to the incoming serial data stream. This Figure shows the recovered clock relationship to the incoming data after CDR lock.

Figure 29-6:      PI Clock Relationship to Data Post CDR Lock

X-Ref Target - Figure 29-6

X15472-phase-interpolator-clk-wave.jpg

For on-chip EyeScan, a replica PI takes in the PI codes from the EyeScan module. The EyeScan PI codes are offset by a particular value from the main IQ PI codes to do a horizontal EyeScan. Thus, the recovered EyeScan clocks are phase shifted from the main recovered IQ clocks by an offset defined by the EyeScan module. This, in combination with the EyeScan samplers, enables 2D EyeScan.