Each APU core includes a physical counter that contains the count value of the system counter. The CNTPCT register holds the current physical counter value. The CNTPCT counter operates in the LPD power domain to provide a reliable and uniform view of the system time to each of the APU cores. This counter is controlled by the TIMESTAMP_REF_CTRL register. The timer is clocked at ½ the APU clock frequency. This logic generates a tick after N clock pulses, where N is defined as:
N = (½ APU clock frequency)/100 MHz.
100 MHz is a configurable clock that goes to the TSGEN module. TSGEN is the timestamp generator in the Coresight™ debug module in the APU and runs between 200 MHz and 400 MHz. The CNTCR register controls the counter operation by enabling, disabling, or halting the counter. Normally, it is 100 MHz after boot, but the frequency can be changed using DBG_TSTMP_CTRL register.