Platform Management and Boot

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU receives requests from other processors to power up and power down peripherals and other units by power sequencing nodes and islands. The PMU also enables and disables clocks and resets.

After a system reset, the PMU ROM pre-boot code initializes the system and the CSU ROM executes the first stage boot loader from the selected external boot device. The boot process configures the MPSoC platform as needed, including the PS and the PL.

After the FSBL execution starts, the CSU enters the post-configuration stage to monitor tamper signals from various sources in the system. The tamper response registers are listed at the bottom of Table: CSU Register Summary.

The system includes many types of security, test, and debug features. The system can be booted either securely (boot image is either encrypted or authenticated, or encrypted and authenticated) or non-securely. Either of the following combinations can be implemented.

Boot image is encrypted.

Boot image is authenticated.

Boot image is both encrypted and authenticated for the highest level of security.

The PL configuration bitstream can be applied securely or non-securely. The boot process is multi-stage and minimally includes the boot ROM and the first-stage boot loader (FSBL). Zynq UltraScale+ MPSoCs include a factory-programmed configuration security unit (CSU) ROM. The boot header determines whether the boot is secure or non-secure, performs some initialization of the system, reads the mode pins to determine the primary boot device, and loads the FSBL.

Optionally, the JTAG interface can be enabled to provide access to the PS and the PL for test and debug purposes.

Power to the PL can be optionally shut off to reduce power consumption. To further reduce power, the clocks and the specific power islands in the PS (for example, an APU power island) can be dynamically slowed down or gated off.