The polygon list builder (PLB) creates lists of the polygons that the pixel processor must draw. For each polygon in a scene, the PLB decides which tiles the polygon covers, and adds the polygon to the lists that draw those tiles. The PLB only adds a polygon to lists where the polygon might have to be drawn, reducing the work involved when the pixel processor renders the scene.
The PLB also discards polygons that are certain not to be visible, based on the following criteria.
•Invalid polygons. For example, any coordinate that is non-numeric, an x or y coordinate that is infinity, or where the area is zero.
•Polygons outside the view frustum.
•Back-facing polygons as defined by the OpenGL ES Common Profile specification.
•Polygons outside the current scissoring box.
The PLB can handle up to 512 lists to support the tile-based rendering mode of the pixel processor efficiently; however, the default is 300. For QVGA or lower resolutions, 300 lists are normally sufficient to make one list for every tile in the scene. For higher resolutions, each list covers multiple tiles. This process is known as binning.
Each list ends with a return command. The driver creates a master tile list containing sets of commands that perform tasks such as beginning new tiles and calling polygon lists. This master tile list is input to the pixel processor polygon list reader.
The PLB requires a variable amount of memory to store the polygon lists. Memory is allocated in blocks of 128, 256, 512, or 1024 bytes, as configured in the GP_PLB_CONF_REG_PARAMS register. Further details are in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].
The driver must allocate the initial memory, consisting of an array of the selected number of polygon lists. More memory is allocated automatically by the PLB from a heap area configured through the GP_PLB_CONF_REG_HEAP_START_ADDR and GP_PLB_CONF_REG_HEAP_STOP_ADDR registers. When this heap is exhausted, an interrupt is generated, and the driver must allocate more memory for the heap.