Port Arbiter

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The port arbiter (PA) block provides latency sensitive, priority-based arbitration between the DRAM commands issued by the XPIs (by the ports). The PA block arbitrates command requests from six AXI ports to the host interface (HIF) of the DDR controller (DDRC). The port arbiter is comprised of multiple tiers of arbitration stages which include the following.