Power Domain Crossing of PLL Clocks

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each system PLL unit has a clock divider in its own power domain and one in the other power domain. Both sets of dividers are represented as boxes in This Figure and the controls for the power-domain crossed clocks are shown in This Figure.

Figure 37-3:      System PLL Clock Power Domain Crossing

X-Ref Target - Figure 37-3

X19869-power-domain-crossing.jpg