Power Islands

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: APU MPCore Power Islands shows the power islands supported by the Cortex-A53 processor.

Table 3-1:      APU MPCore Power Islands

Power Island

Description

CORTEXA53

Includes the SCU, the L2 cache controller, and the debug registers that are described as being in the debug domain. This domain is a part of the PS full-power domain (FPD).

PDL2

Includes the L2 cache RAM, L2 tag RAM, L2 victim RAM, and the SCU duplicate tag RAM.

PDCPU[4]

This represents core 0, core 1, core 2, and core 3. It includes the advanced SIMD and floating-point extensions, the L1 TLB, L1 cache RAMs, and debug registers.