Power Management

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PCIe protocol specification indicates four low-power states: L0s, L1, L2, and L3, with L0s having the least recovery latency (shallow-power state) and L3 having the maximum recovery latency as it involves possible power supply turn-off (deep-power state). L0 is the normal working link state. In addition to the L0 state, the integrated block for PCIe supports the L1 (low power) state. Entry into L1 from L0 needs to be initiated by the software.

Note:   The integrated block for PCIe does not support active state power management (ASPM). ASPM L0s support is optional per the PCI-SIG ASPM Optionality ECN [Ref 55].