Power Management in GPU

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
Release Date
2.3 English

The GPU acts as a slave with respect to the power management. Another processor runs the GPU device driver and responsible for managing the GPU’s overall power including the power down of the pixel processors.

All sub-blocks within the GPU (pixel processor, geometry processor, or the L2 controller) include an idle signal that is routed to the FPD_SLCR.GPU register containing the PP{0, 1} and GPU idle indicators. Before requesting the PMU to power down the GPU PP0 or PP1, the GPU device driver must check the FPD_SLCR.GPU [PPx_Idle] bits to ensure that the targeted pixel processor is idle.

The device driver then requests the PMU to power down the pixel processor by writing 1 to the [PP0] or [PP1] bit in the PMU_GLOBAL.PWR_STATE register. The pixel processor power state is indicated in the PMU_GLOBAL.PWR_STATE register.

Similarly, the device driver can initiate the power up of a GPU pixel processor by setting the bit associated with the target pixel processor in the Power_Up_Request register, which triggers the PMU to proceed with powering up the target GPU pixel processor. The request to release the reset on the GPU or its associated pixel processors must be explicitly requested by the device driver by setting the appropriate bits in the PMU Reset_Request register as explained in the PMU Reset section of Platform Management Unit. Chapter 6 also has information on the Power_Down_Request and Power_Up_Request registers.