Power Pins

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The dedicated power pins for the PS and internal logic of the PL are listed in Table: Power Pins. See Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2] for specifications.

Table 2-1:      Power Pins

Pin Name

Description

VCC_PSINTLP

PS low-power domain (LPD) supply voltage.

VCC_PSINTFP

PS full-power domain (FPD) supply voltage.

VCC_PSAUX

PS auxiliary voltage.

VCC_PSBATT

PS battery operated voltage.

VCC_PSPLL

LPD PLLs: RPLL (RPU), IOPLL (I/O).
FPD PLLs: APLL (APU), VPLL (video), DPLL (DDR controller).

VCC_PSDDR_PLL

DDR PLLs supply voltage for DDRIOB. Tie to ground.

VCC_PSINTFP_DDR

DDR memory controller supply voltage. Tie to ground.

VCCO_PSDDR

PS DDR I/O supply voltage. Tie to ground.

VCCO_PSIO[0:3]

Power supply voltage for the PS I/O banks.

VCCO_PSIO[0] is bank 500. MIO pins 0 to 25.

VCCO_PSIO[1] is bank 501. MIO pins 26 to 51.

VCCO_PSIO[2] is bank 502. MIO pins 52 to 77.

VCCO_PSIO[3] is bank 503. Mode, config, PSJTAG, error, SRST, POR, PS_REF_CLK.

VCCINT

PL power domain (PLPD) supply voltage.

VCCINT_VCU

Video codec unit supply voltage.

VCCAUX

PL auxiliary voltage.

VCCBRAM

PL block RAM supply voltage.

PS_MGTRAVCC

PS-GTR VMGTAVCC supply voltage.

PS_MGTRAVTT

PS GTR VMGTAVTT termination voltage.

VCC_PSADC

PS System Monitor analog voltage.

VCCADC

PL System Monitor analog voltage.