Power Saving Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR memory controller supports various methods to save power within the system in different modes: Precharge power-down, self-refresh, deep power-down, maximum power saving, and disabling clock to the SDRAM using PWRCTL.en_dfi_dram_clk_disable.

In multi-rank systems, these power-saving modes cannot be applied on a per-rank basis. If applied, they are always applied globally. When enabled, the controller automatically enters and exits precharge power-down mode based on a programmable idle timeout period. Self-refresh can be entered/exited using the following approaches.

Based on a programmable idle timeout period (similar to precharge power-down idle timeout).

Software controlled.

Hardware low-power interface(s).

Deep power-down (DPD) and maximum power saving mode (MPSM) entry and exit are explicitly controlled by you. In addition, the clock to the SDRAM can be disabled by setting the PWRCTL.en_dfi_dram_clk_disable bit.

This can be done in the following modes:

Self-refresh.

Self-refresh power down (LPDDR4 only).

Power-down.

Deep power-down.

Maximum power saving mode.

 

IMPORTANT:   Do not enable more than one of the following power-saving modes simultaneously.

Deep power-down.

Maximum power saving mode.

You can enable any combination of power-down and self-refresh modes simultaneously.

Power-down: PWRCTL[powerdown_en]=1.

Automatic self-refresh: PWRCTL[selfref_en]=1.

Software self-refresh: PWRCTL[selfref_sw=1.

Enabling the assertion of the PWRCTL[en_dfi_dram_clk_disable] bit is valid in combination with any of the power-saving modes.