Power Up

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Any master in the system can queue a request to the PMU to power up an island or domain by writing a 1 to the appropriate bits in the REQ_PWRUP_TRIG register. If a 1 is also written to the same bit in the REQ_PWRUP_INT_MASK register, the PMU will be interrupted. After executing the preamble ISR to check the interrupt pending register within the I/O block, it will execute the power-up request ISR. The priority of the power up is enforced such that domains are powered up first, then the islands, followed by slaves, and then finally the masters.