Power and Reset

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DDR memory controller is powered by the VCC_PSINTFP_DDR pins. These pins must be connected to the VCC_PSINTFP power pins and the FPD power supply. The DDR memory controller can only be reset along with the FPD using the PMU_GLOBAL.GLOBAL_RESET [FPD_RST] reset bit.

Note:   Once the initial calibration sequence in psu_init.c is completed Xilinx-AMD does not recommend using RST_DDR_SS to reset the DDR subsystem.