The JTAG debug port (JTAG-DP) provides a few signals for conveniently requesting for power-on from the debugger. Further details are provided in the CoreSight SoC-400 System Design Guide [Ref 41]. The following is a summary.
Powering up both is required as the first step of debugging via CoreSight. Each pair consists of a request and an acknowledgment, and can be used to communicate to the PMU. Although they were originally intended to be used for debug power domain and system power domain, they are used instead as follows.
°Controlled by CTRL/STAT[29:28] register bits of JTAG-DP
°Used to power up the two Cortex-R5F MPCore CPU islands
°Controlled by CTRL/STAT[31:30] register bits of JTAG-DP
°Used to power up the entire FPD