Precision Time Protocol via EMIO

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PTP signals connected to the Ethernet controller provide the capability to handle IEEE-1588 precision time protocol (PTP) signaling.

Table 34-16:      IEEE 1588 PTP frame recognition and Time Stamp Unit

Signal Name

I/O

Description

sof_tx

O

Asserted high synchronous to tx_clk when the SFD is detected on a transmit frame, deasserted at end of frame.

sync_frame_tx

O

O Asserted high synchronous to tx_clk if PTP sync frame is detected on transmit.

delay_req_tx

O

Asserted high synchronous to tx_clk if PTP delay request frame is detected on transmit.

pdelay_req_tx

O

Asserted high synchronous to tx_clk if PTP peer delay request frame is detected on transmit.

pdelay_resp_tx

O

Asserted high synchronous to tx_clk if PTP peer delay response frame is detected on transmit.

sof_rx

O

Asserted high synchronous to rx_clk when the SFD is detected on a receive frame.

sync_frame_rx

O

Asserted high synchronous to rx_clk if PTP sync frame is detected on receive.

delay_req_rx

O

Asserted high synchronous to rx_clk if PTP delay request frame is detected on receive.

pdelay_req_rx

O

Asserted high synchronous to rx_clk if PTP peer delay request frame is detected on receive.

pdelay_resp_rx

O

Asserted high synchronous to rx_clk if PTP peer delay response frame is detected on receive.

tsu_clk

I

Alternative clock source for the time stamp unit. If gem_tsu_clk is defined in the gem_defs.v file then the TSU is clocked by tsu_clk rather than pclk. This clock must have a frequency greater than 1/8th the frequency of tx_clk or rx_clk. Timestamp accuracy improves with higher frequencies.

gem_tsu_ms

I

TSU master/slave. Used with gem_tsu_inc_ctrl to control incrementing of the TSU and loading the sync strobe register.

gem_tsu_inc_ctrl[1:0]

I

Used to control incrementing of the TSU and synchronous to tsu_clk or pclk. Drive high when not being used.

tsu_timer_cnt[93:0]

O

TSU timer count value, synchronized to tsu_clk or pclk.

Upper 48 bits are seconds value and lower 46 bits are nanoseconds / sub-nanoseconds. Bit 46 toggles every second, i.e. 1 pps.

tsu_timer_cmp_val

O

TSU timer comparison valid, synchronized to tsu_clk or pclk. Asserted high when upper 70 bits of TSU timer count value is equal to programmed comparison value.

There are three different TSU clock sources allowed:

Internal PLL

To enable clock source via internal, PLL GEM_CLK_CTRL bit[21:20] should be 0b00 and TSU_REF_CLK_CTRL bit[24] should be 1, along with appropriate clock source and divisor fields. This mode required no additional signal connections in the design and no additional configuration in Vivado block.

Via MIO 50 or 51

To enable clock source via internal, MIO 50/51 GEM_CLK_CTRL bit[21:20] should be 0b11 and TSU_REF_CLK_CTRL bit[24] should be 0. MIO_PIN_50/51 register should be configured for tsu. The selected MIO signal should be connected on board to an appropriate TSU clock source. The value of this should be specified in the Vivado clock configuration.

Via EMIO

To enable clock source via internal, PLL GEM_CLK_CTRL bit[21:20] should be 0b11 and TSU_REF_CLK_CTRL bit[24] should be 0. MIO_PIN_50/51 register should NOT be configured for tsu (so the clock is automatically picked from EMIO). Connect emio_enet0_tsu_clk to the appropriate TSU clock source on board.

Additional TSU signal configuration:

Whenever exposed in the Vivado design, it is recommended to loop the feedback signals fmio_gem_tsu_clk_to_pl_bufg and fmio_gem_tsu_clk_from_pl.

Whenever exposed, gem_tsu_inc_ctrl[1:0] SHOULD BE tied to 0b11 in order for GEM TSU to increment normally and function as a PTP slave.