Priority Queuing

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA is configured to use packet buffer memories. The GEM_GXL can optionally select two priority queues, q and q1. Each queue has an independent list of buffer descriptors pointing to separate data streams.

In the transmit direction, higher priority queues are always serviced before lower priority queues. This priority scheme requires the user to ensure that high priority traffic is constrained so that lower priority traffic will have the required bandwidth.

The DMA determines the next queue to service by initiating a sequence of buffer descriptor reads interrogating the ownership bits of each. The buffer descriptor corresponding to the highest priority queue is read first. If the ownership bit of this descriptor is set, then the DMA will progress to reading the second highest priority queue's descriptor.

If all the descriptors return an ownership bit set a resource error has occurred. An interrupt is generated and transmission is automatically halted. Transmission can only be restarted by setting the START bit in the network control register. The DMA will identify the highest available queue to transmit from when the START bit in the network control register is written to and the TX is in a halted state or when the last word of any packet has been fetched from external AHB or AXI memory.

The following sequence illustrates how to route receive packets to q or q1.

Note:   In this case, filtering received packets based on ether type value (in this case IPv4) and routing matching packets to queue1 and rest of the packets to queue0.