Private CPU Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are separate private CPU registers for the RPUs and APUs to program the interrupt controllers. The addresses are shown in Table: CPU Private Registers. The APU_GIC is located on the AXI interconnect and can be made exclusively accessible to the APU by using the FPD_XMPU protection unit.

Table 10-5:      CPU Private Registers

Register Base Address

Description

0xF900_0000 to 0xF900_1FFF

GIC distributor.

0xF900_2000 to 0xF900_2FFF

GICC interface.

0xFD6E_0000 to 0xFD6E_FFFF

CCI_GPV (CCI400, parameters)

0xFD70_0000 to 0xFD7F_FFFF

FPD_GPV (parameters)

0xFE00_0000 to 0xFE0F_FFFF

IOU_GPV (parameters)

0xFE10_0000 to 0xFE1F_FFFF

LPD_GPV (parameters

0xFD80_0000 to 0xFDFF_FFFF

SMMU_GPV (SMMU500, parameters)

Note:   The generic CPU timer, L2 cache, and SCU (etc.) in the APU can only be accessed through co-processor instructions, they are not memory mapped.