Program the AFMR and AFIR Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The valid AFMR and AFIR register bit fields for sending TX messages to the controller are summarized in Table: CAN Message Acceptance Mask and Identifier Register Bit Fields. These fields are described in the Message Format section.

Table 20-5:      CAN Message Acceptance Mask and Identifier Register Bit Fields

AFMR{1:4} Registers

AFIR{1:4} Registers

[AMRTR]

[AIRTR]

[AMIDL]

[AIIDL]

[AMIDE]

[AIIDE]

[AMSRR]

[AISRR]

[AMIDH]

[AIIDH]

Standard frame

Set = 0

Set = 0

Valid

Valid

Valid

Extended frame

Valid

Valid

Valid

Valid

Valid

In the AFMR mask registers, enable (unmask) the compare functions for each field for the incoming RX message by writing a 1 to the bit field. In the AFIR registers, write the values that are to be compared to the incoming TX message.