Program the DDR XMPUs

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are six DDR, one FPD, and one OCM memory protection units. Four of the DDR XMPUs are not used in this programming example (all of the other XMPUs are used).

Disable the unused DDR XMPU units by setting the [DefWrAllowed] and [DefRdAllowed] bit fields to “not allowed” and leave the region registers R{00:15}_{START, END, MASTER, CONFIG} in their reset state.

Write 0h to the DDR_XMPUx_CFG.CTRL registers (units 0, 3, 4, and 5).

Program two DDR XMPU units (1, 2} for the two parallel AXI channels from the CCI to the DDR memory controller. For this example, they are programmed in the same manner.

1.Disallow default accesses for all regions. Write 8h to the DDR_XMPUx_CFG.CTRL registers.

2.Program a set of region configuration registers for secure reads and writes to the first GB of DDR memory by any of the APU cores.

a.Write 0007h to the DDR_XMPUx_CFG.R00_CONFIG register for ports 1 and 2.

b.Write 0000h to the DDR_XMPUx_CFG.R00_START register for ports 1 and 2.

c.Write 03FFh to the DDR_XMPUx_CFG.R00_END register. The memory region for the DDR XMPU units is 1-MB aligned so bits [19:0] are always 0h and bits [39:20] are programmed. The resulting end address is 0x0_3FF0_0000 plus the block size. The result is 0x0_3FFF_FFFF for a total of 1 GB.

d.Write 00C0_0080h to the DDR_XMPUx_CFG.R00_MASTER register. To allow only the APU cores to access the DDR memory, the [MASK] bit field is set to C0h and the [ID] bit field is set to 80h. See Table: Master ID List Entry for the list of Master ID numbers and equation This Equation for the comparison testing done by the controller.

Note:   Additional, high-order Master ID bits could be tested, but that is unnecessary for these DDR protection units because no other master with similar ID bits has access to the DDR XMPU{1, 2} units.

Note:   To enable additional masters to access the DDR memory region via the CCI, including the DMA units in the GEM and PCIe controllers, then program additional sets of region registers using their Master IDs and the desired memory range.