Program the FPD XMPU

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Program the FPD XMPU so that it only allows the APU to access the SATA AHCI registers with secure reads and writes in a 64-KB memory region.

1.Disallow default accesses for all regions. Write 0h to the FPD_XMPU_CFG.CTRL register.

2.Program a set of region registers.

a.Write 0007h to the FPD_XMPU_CFG.R00_CONFIG register. If strict secure/non-secure checking is desired, write 0017h instead.

b.Write 0F_D0C0h to the FPD_XMPU_CFG.R00_START register. The memory region for the FPD XMPU unit is 4-KB aligned so bits [11:0] are always 0h and address bits [31:12] are programmed. The resulting start address is 0xFD0C_0000; the start of the OCM memory.

c.Write 0F_D0CFh to the FPD_XMPU_CFG.R00_END register. The end address is 0xFD0C_F000 plus the last block. The result is 0xFD0C_FFFF.

d.Write 02C0_0080h to the FPD_XMPU_CFG.R00_MASTER register. To allow only the APU cores to access the SATA AHCI registers, the [MASK] bit field is set to 2C0h and the [ID] bit field is set to 080h. Refer to Table: Master ID List Entry for the list of Master ID numbers and This Equation for the comparison testing done by the controller.

Note:   These [ID] and [MASK] bit field settings are more selective than the DDR XMPU settings because the DDR XMPUs have additional AXI masters with access to the AXI channels protected by these protection units.