Program the OCM XMPU

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Program the OCM XMPU so that it allows the RPU to access the first 64 KB of the OCM memory region with secure read and write transactions.

1.Disallow default accesses for all regions. Write 0h to the OCM_XMPU_CFG.CTRL register.

2.Program a set of region registers.

a.Write 0007h to the OCM_XMPU_CFG.R00_CONFIG register. If strict secure/non-secure checking is desired, write 0017h instead.

b.Write 0F_FFC0h to the OCM_XMPU_CFG.R00_START register. The memory region for the FPD XMPU unit is 4-KB aligned so bits [11:0] are always 0h and address bits [31:12] are programmed. The resulting start address is 0xFFFC_0000; the start of the OCM memory.

c.Write 0F_FFCFh to the OCM_XMPU_CFG.R00_END register. The end address is 0xFD0C_F000 plus the last block; the result is 0xFD0C_FFFF.

d.Write 02C0_0080h to the OCM_XMPU_CFG.R00_MASTER register. To allow only the APU cores to access the SATA AHCI registers, the [MASK] bit field is set to 2C0h and the [ID] bit field is set to 080h. Refer to Table: Master ID List Entry for the list of Master ID numbers and This Equation for the comparison testing done by the controller.