Program the XPPU

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This example configures two AXI masters and two 64 KB apertures in the XPPU.

RPU0 permitted to access the I2C0 controller.

APU permitted to access the GEM registers.

This is a two-step process that establishes two masters using the MASTER_IDxx registers and two 64-KB aperture registers.

Configure two masters: the master ID [MID] and mask [MIDM] bit fields identify the master using This Equation.

1.Configure the APU as master 0. Write 02C0_0080 to the MASTER_ID00 register.

2.Configure the RPU0 as master 1. Write 02C0_0000 to the MASTER_ID01 register.

Note:   The first eight MASTER_IDxx registers are predefined by reset, but they can be overwritten and configured for any master.

Program two 64-KB Apertures: one each for access to the GEM0 and I2C0 registers.

The GEM0 registers are mapped to 0xFF0B_0000. Access is controlled by the APERPERM_011 register at 0xFF98_102C.

Configure aperture 11 for APU access. Write 0_0001h (enable bit for master 0) to the APERPERM_011 [PERMISSION] bit field.

The I2C0 registers are mapped to 0xFF02_0000. Access is controlled by the APERPERM_002 register at 0xFF98_1008.

Configure aperture 2 for RPU0 access. Write 0_0002h (enable bit for master 1) to the APERPERM_002 [PERMISSION] bit field.

Note:   The aperture registers include two other fields. The [TRUSTZONE] bit would be set to 0 in this example to ensure only secure transactions are allowed and the [PARITY] bit needs to be calculated and written to ensure data integrity.

Enable XPPU permission and parity checking: the XPPU control register includes permission and parity checking enables.

1.Enable the XPPU unit. Write a 1 to the CTRL [ENABLE] bit.

2.Optionally enable parity for the master configuration registers {00:19}. Write a 1 to the CTRL [MID_PARITY_EN] bit.

3.Optionally enable parity for the aperture registers {000:400}. Write a 1 to the CTRL [APER_PARITY_EN] bit.

Note:   Parity errors are signaled by the ISR [MID_PARITY] and [APER_PARITY] status bits.