Programmable Clock PL Throttle

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The four generated clocks for the PL (PL_REF_CLKx) have clock throttling logic associated with each clock. By default, clock throttling is off and there is continuous clock output. For each of the clocks throttle logic, there are two registers.

PL0_THR_CTRL: PL clock threshold control and status.

PL0_THR_CNT: PL clock threshold count value.

The throttle behavior is controlled by indicating a desired number of clock pulses by writing a 16-bit value to the PL0_THR_CNT register. For example, if PL0_THR_CNT is set to 0, then the output is free running. If there is a programmed value, then the output is clocked using the number indicated in this register.

The output clock counting can be started or triggered by writing to the CPU_START bit of the PL0_THR_CTRL register. The output clock can also be halted by the PLx_THR_STOP signal from the PL logic when the counting mechanism is turned on. This pin stops the PL clock during PL logic debug.

The register PL0_THR_CTRL[CURR_VALUE] counts the amount of clocks produced since CPU_START was initiated.