Programmed Power Management

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

To achieve considerable power savings on the PCI Express hierarchy tree, the core supports these link states of the programmed power management (PPM).

L0: Active state, data exchange state.

L1: Higher latency, lower power standby state.

The PPM protocol is initiated by the downstream component/upstream port.

PPM L0 state

The L0 state represents normal operation and is transparent to your logic. The core reaches the L0 state after a successful initialization and training of the PCI Express link as per the protocol.

PPM L1 state

The following steps outline the transition of the core to the PPM L1 state.

a.The transition to a lower power PPM L1 state is always initiated by an upstream device by programming the PCI Express device power state to non-D0 (in the PM capability in configuration register space). The current device power state can be read through APB registers.

b.The integrated block for PCIe stops accepting any further transactions. Any pending transactions are accepted fully and completed later.

c.The integrated block for PCIe exchanges appropriate power management data link layer packets (DLLPs) with its link partner to successfully transition the link to a lower power PPM L1 state.

d.All transactions are stalled for the duration of time when the device power state is non-D0.

 

TIP:   After identifying the device power state as non-D0, the software logic can initiate a request through the cfg_pm_wake to the upstream link partner to configure the device back to the D0 power state. If the upstream link partner has not configured the device to allow the generation of PM_PME messages (cfg_pmcsr_pme_en = 0), the assertion of cfg_pm_wake is ignored by the core. See the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].