Programming Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The following steps describe the sequence of operations to program the PCI Express controller.

1.Program the CRF_APB.RST_FPD_TOP register to release pcie_cfg_rst, gt_rst, and pcie_bridge_reset.

2.Program the CRF_APB.PCIE_REF_CTRL register to activate the clock. The minimum required values for 250 MHz are set as default divisor values. Frequencies that are less than 250 MHz can have performance implications.

3.Program the integrated block for PCIe to Endpoint or Root Port role using the APB interface. The default values in registers are for an Endpoint mode of operation.

4.For the Root Port mode operation, program the following.

a.Set the BAR and the memory base/limit registers to defaults for the Root Port, as documented in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

PCIE_ATTRIB.ATTR_7   = 0x0    
PCIE_ATTRIB.ATTR_8   = 0x0    
PCIE_ATTRIB.ATTR_9   = 0x0    
PCIE_ATTRIB.ATTR_10   = 0x0    
PCIE_ATTRIB.ATTR_11   = 0xFFFF   
PCIE_ATTRIB.ATTR_12   = 0xFF   
PCIE_ATTRIB.ATTR_13   = 0x0   
PCIE_ATTRIB.ATTR_15   = 0xFFF0   
PCIE_ATTRIB.ATTR_16   = 0xFFF0   
PCIE_ATTRIB.ATTR_17   = 0xFFF1   
PCIE_ATTRIB.ATTR_18   = 0xFFF1

PCIE_ATTRIB.ATTR_101 [ATTR_DISABLE_BAR_FILTERING] = 0x1 (this setting is specific to RP mode).

Note:   For EP mode, BAR settings are dependent on user selection such as size, prefetchable or not, etc.

b.Change the class code.

PCIE_ATTRIB.ATTR_24 [ATTR_CLASS_CODE] = 0x400   
PCIE_ATTRIB.ATTR_25 [ATTR_CLASS_CODE] = 0x6

c.Change the header to type-1.

PCIE_ATTRIB.ATTR_34 [ATTR_HEADER_TYPE] = 0x1
PCIE_ATTRIB.ATTR_100 [ATTR_UPSTREAM_FACING] = 0x0

d.Change the device port type to Root Port.

PCIE_ATTRIB.ATTRIB_50 [ATTR_PCIE_CAP_DEVICE_PORT_TYPE] = 0x4

e.Change the Next pointer for PM capability to point to PCIe capability.

PCIE_ATTRIB.ATTRIB_53 [ATTR_PM_CAP_NEXTPTR] = 0x60

f.Disable the MSI capability.

PCIE_ATTRIB.ATTRIB_41 = 0x0

g.Enable the routing of various message TLPs to the bridge from the integrated block for PCIe.

PCIE_ATTRIB.ATTRIB_101 [ATTR_ENABLE_MSG_ROUTE] = 0x7FF

h.Set the credits to defaults, as documented in the register database.

PCIE_ATTRIB.ATTR_105 [ATTR_VC0_TOTAL_CREDITS_CD] = 0xCD
PCIE_ATTRIB.ATTR_106 [ATTR_VC0_TOTAL_CREDITS_CH] = 0x24
PCIE_ATTRIB.ATTR_106 [ATTR_VC0_TOTAL_CREDITS_NPH] = 0xC
PCIE_ATTRIB.ATTR_107 [ATTR_VC0_TOTAL_CREDITS_NPD] = 0x18
PCIE_ATTRIB.ATTR_108 [ATTR_VC0_TOTAL_CREDITS_PD] = 0xB5
PCIE_ATTRIB.ATTR_109 [ATTR_VC0_TOTAL_CREDITS_PH] = 0x20

i.CRS SW visibility is specific to RP mode.

PCIE_ATTRIB.ATTR_79 [ATTR_ROOT_CAP_CRS_SW_VISIBILITY] = 0x1

5.Program CRF_APB.RST_FPD_TOP to release pcie_ctrl_rst.

At this point, the controller is ready to initiate link training with a link partner, if pcie_reset_n (PERST#) is released by the board or the host.

Note:   When using the Xilinx delivered tool flow, the attributes for Endpoint or Root Port mode operation are set by the first-stage boot loader.