Programming Example

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This programming example includes the XPPU and XMPU programming steps for the RPU and APU to permit secure read and write access to several system elements in the following system configuration:

The APU is the master of these system elements:

°DDR memory space: DDR XMPU, first 1 GB of memory.

°GEM0 control registers: XPPU aperture.

°SATA AHCI registers: FPD XMPU, a 64 KB region.

The RPU is the master for these system elements:

°OCM memory space: OCM XMPU, first 64 KB of memory.

°I2C0 control registers: XPPU aperture.

Note:   The memory regions can be configured for read-only/write-only or non-secure access based configuration parameters.

Note:   The Vivado Design Suite generates first stage bootloader (FSBL) code to program the XMPU and XPPU based on the design defined by the processor configuration wizard (PCW).

The XMPU and XPPU register sets are listed in Table: XMPU Register Summary and Table: XPPU Register Summary.