Programming Examples

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The programming sequence for the PLL units require careful consideration for the oscillator based on the desired output frequency controlled by [FBDIV] and other parameters. Each PLL unit has three control registers:

xPLL_CTRL [RESET, BYPASS, FBDIV, DIV2, PRE_SRC, POST_SRC]

xPLL_CFG [RES, CP, LFHF, LOCK_CNT, LOCK_DLY]

xPLL_FRAC_CFG [DATA, ENABLED]

Helper data is programmed into the xPLL_CFG registers. See PLL Integer Divide Helper Data Table for information on the helper data in the integer and fractional modes.