Programming Modes

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section outlines the circumstances under which the DDRC registers can be written. Most registers are initialized when the DDRC core is in reset (core_ddrc_rstn = 0) and should not need to be changed afterwards. The exceptions are listed in the following sections. The core_ddrc_core_clk should be brought up and running before the DDRC core is brought out of reset (core_ddrc_rstn is deasserted).

The DDRC register programming modes are described in the Zynq UltraScale+ MPSoC Register Reference UG1087 [Ref 4]. In UG1087, registers are described as static, dynamic, dynamic - refresh related, or quasi dynamic.