Programming Reset Pin

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Program the MIO registers in the IOU_SLCR module to configure the PCIe reset pin. For the Endpoint port, the PCIe reset pin is configured as an input. For the Root Port, it is configured as an output.

For the Endpoint port, use one of MIO_PIN_[29,30,31,33,34,35,36,37] from the IOU_SLCR module as PCIe reset input (based on board layout). The input reset signal is listed in table Table: PCIe Reset Signals on MIO.

For the Root Port, use any GPIO to map the reset output, which is driven by software.