Programming and Usage Considerations

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The generic Quad-SPI controller supports two operating modes: I/O mode and the DMA mode.

In I/O mode, which supports all types of memory operations, the SPI memory instructions are sent to the generic FIFO at 0x00000140 and the program data is sent to a fixed offset address of 0x0000011C. The read data or status is retrieved from a fixed offset address of 0x00000120, 0x0000010C. The software is responsible for providing the SPI instruction and handling data formatting, and alignment. The generic Quad-SPI controller is responsible for managing the low-level signaling.