Programming the PS-GTR Transceiver

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The following steps are used to program the PS-GTR transceiver interface to support the PCI Express protocol. For more information on the PS-GTR transceiver interface, refer to PS-GTR Transceivers.

1.Assign SerDes lanes to the PCIe PHY that presents a PIPE interface to the controller for PCIe.

2.Program SERDES.ICM_CFG0 and SERDES.ICM_CFG1 to support the PCIe protocol lanes as per the requirement (Table: PS-GTR Multiplexer Configuration for PCI Express Lanes).

Table 30-15:      PS-GTR Multiplexer Configuration for PCI Express Lanes

PCI Express Lane Configuration

Registers to program

Comments

x1

SERDES.ICM_CFG0[L0_icm_cfg] = 1

Other 3 lanes (L1, L2, L3) can be used by other protocols like SATA, DisplayPort, USB, GEM.

x2

SERDES.ICM_CFG0[L0_icm_cfg] = 1

SERDES.ICM_CFG0[L1_icm_cfg] = 1

Other 2 lanes (L2, L3) can be used by other protocols like SATA, DisplayPort, USB, GEM.

x4

SERDES.ICM_CFG0 = 0x0011

SERDES.ICM_CFG1 = 0x0011

All lanes are assigned to PCIe protocol.

3.Set the PLL reference clock to 100 MHz: SERDES.PLL_REF_SEL0 = 0x0D