QoS Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section does not attempt to describe the full details of the QoS controller operation, but describes the high-level functions as they relate to the system QoS.

One of the issues with isochronous traffic passing through the interconnect is that the timeout associated with the transaction only starts to run once the transaction enters the DDR controller. If a transaction was trapped just outside of the DDR controller, behind another transaction (perhaps due to the system being very heavily utilized), that transactions’ timer would not be running. When the transaction eventually enters the DDR controller, it starts its timer running, but does not account for the elapsed time it has waited, while sitting just outside the controller. The result is that the timeout is inaccurate and fails to meet the needs of the programmed isochronous maximum latency.

One of the aims of the QoS controller is to ensure that there is space available in the memory controller CAMs for isochronous traffic at all times. It achieves this goal by monitoring the CAM levels and throttling the XPI port.