This Figure shows how the traffic from the low-latency and best-effort masters goes to port 1 and port 2 of the DDR memory controller through the CCI-400. The CCI-400 has three master ports, two are connected to the DDR memory controller. To avoid head-of-line blocking (HOLB) on the DDR memory controller ports, the CCI-400 does not mix the best-effort traffic with low-latency traffic. This is possible because the CCI-400 allows access to the complete DDR memory through both master ports.
When both low-latency and best-effort masters try to read from the same DDR memory region that is allocated to one of the master ports of the CCI-400, a mix of best-effort and low-latency traffic can be present on that particular port of the DDR memory controller. This mix can lead to head-of-line blocking on that port. To avoid a HOLB issue, the QoS virtual networks (QVN) feature is used inside the CCI-400. The QVN-aware slave is implemented to talk with the CCI-400 QVN enabled master ports.
As shown in This Figure, there are two queues per port structure in the QoS controller. The red queue is mapped to low-latency traffic and the blue queue is mapped to best-effort traffic based on the AxQoS signal values. The QVN logic implementation details are listed.
•The low-latency and best-effort credit counters indicate the depth of the queue.
•When there is space available in the queue and a master virtual network requests a token, then grant the token and reduce the credit counter.
•Once the transaction is in queue, it waits until the DDR memory controller port arbitration accepts the read command.
•Once the arbitration accepts the read command, the respective pop signal is asserted.
•Assertion of the low-latency/best-effort queue command pop signal increases the respective credit counter.
•After the previous steps, the logic stops issuing a QVN token when the respective read command queue is full.
•The Push signal indicates that the master is requesting a token on the virtual channel.
•Push_Enable indicates that there is room available in the queue and a token can be issued.
The QVN issues credit from the credit counter (this counter size is the same as the XPI queue depth) to the master when there is space in the XPI queue. Once credit is issued, the credit counter is decremented. When the pop signal is asserted, the transaction is popped from the XPI and the credit counter is incremented to return the credit.