Quad-SPI Feedback Clock

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Quad SPI interface has an optional feedback clock pin named clk_for_lpbk. The clk_for_lpbk pin is not used for loopback mode. The internal clock is used for loopback mode. The loopback mode is used with the high-speed Quad SPI timing mode, where the memory interface clock needs to be greater than 40 MHz. The feedback signal is received from the internal input from the I/O. So, MIO pin 6 should be programmed and allowed to toggle freely.

Based on the tap delay value programmed, the internal clock is delayed and used for capturing the data. See Quad-SPI Tap Delay Values for programming the tap values for different operation frequencies.This pin (MIO 6) is not driven from outside and should be left floating in QSPI clock feedback mode. In QSPI non-clock feedback mode, the pin is not used by the QSPI, so it can be used as a peripheral I/O (GPIO, CAN, I2C, and so on).