The recommended clock and data tap delay values should be programmed based upon the frequency of operation. Refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2] and Answer Record 72797 for information on I/O timing.
At 40 MHz, the Quad-SPI controller should be in non-loopback mode with the clock and data tap delays bypassed. The register settings are shown in Table: Quad-SPI Controller at 40 MHz Tap Delay Value. These are default values and are applicable for both generic and legacy modes.
At 100 MHz, the Quad-SPI controller should be in clock loopback mode with the clock tap delay bypassed, but the data tap delay enabled. The register settings are shown in Table: Quad-SPI Controller at 100 MHz Tap Delay Value. These values are applicable for both generic and legacy modes.
Note: The taps mentioned here refer to non-PVT compensated delay elements. Programmable delay elements are provided on incoming data and on sampling clock to delay data or sampling clock signals. The value of these taps should not be changed dynamically.
At 150 MHz, only the generic controller can be used. The generic controller should be in clock loopback mode and the clock tap delay enabled, but the data tap delay disabled. The register settings are shown in Table: Generic Quad-SPI Controller at 150 MHz Tap Delay Values.
Note: The legacy Quad-SPI controller does not support 150 MHz frequency.