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Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The interconnect is built using the Arm NIC400 IP. This Figure shows the high-level block diagram of the interconnect switch hierarchy. There are six independent AXI ports on the DDR controller. In some cases, traffic classes are physically separated on the interconnect using different paths.

The AXI interconnect supports all the AXI4 signals. For some AXI masters, the interconnect provides registers for programming the value of the ArQoS and AwQoS bits.

The PL AXI masters include the following options.

Static QoS: For programming the value of the AxQoS bits using the AFIFM.RDQoS registers.

Dynamic QoS: The PL master can drive the QoS bits on a per transaction basis.

The NIC400 IP (interconnect) uses the following AxQoS bits for arbitration.

AxQoS[3:0] is used to indicate the priority of the request. An 0xF is the highest priority and an 0x0 is the lowest priority.

In the event that more than one requester has the same AxQoS priority value, the NIC400 reverts to a least recently granted arbitration scheme to break the tie.