Quasi Dynamic Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In addition to the dynamic registers, the following categories of registers can be written after reset:

Group 1: registers that can be written when no Read/Write traffic is present at the DFI.

Group 2: registers that can be written in self-refresh, DPD, and MPSM modes.

Group 3: registers that can be written when the controller is empty.

Group 4: registers that can be written depending on MSTR.frequency_mode and the MSTR2.target_frequency.

Each category requires specific conditions for the registers to be programmed. Once the programming conditions are met, the SWCTL.sw_done register must be programmed to 1’b0 to enable the software programming.

Once the programming is completed, the SWCTL.sw_done must be set to 1’b1 and the SWSTAT.sw_done_ack must be read as 1’b1 to ensure that the quasi dynamic registers are propagated correctly to the destination clocks.

Traffic must be enabled again depending on the register category as described in the following sections.