RPU GIC Interrupt Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

There are two interfaces between the RPU MPCore and the RPU GIC.

Distributor interface is used to assign the interrupts to each of the Cortex-R5F MPCore processors.

CPU interface with a separate set of 4 KB memory-mapped registers for each CPU. This provides protection against unwanted accesses by one CPU to interrupts that are assigned to the other.

The APU MPCores processors access the RPU_GIC interrupt controller (This Figure) through their peripheral interface. The low-latency peripheral interfaces are really designed for strongly ordered or device type accesses, which are restrictive by nature. Memory that is marked as strongly ordered or device type is typically sensitive to the number of reads or writes performed. Because of this, instructions that access strongly ordered or device memory are never abandoned when they have started accessing memory. These instructions always complete either all or none of their memory accesses. The same is true of all accesses to the low-latency peripheral port, regardless of the memory type.

Figure 13-2:      RPU Interrupt Controller Block Diagram

X-Ref Target - Figure 13-2

X15328-rpu-interrupt-controller.jpg