RPU Pin Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The following table describes the real-time processor configuration signals.

Table 4-1:      RPU Pin Configuration

Pins

Selection

Description

VINITHIm

SLCR configurable (default 1)

Reset V-bit value. When High indicates HIVECS mode at reset.

CFGEE

SLCR configurable (default 0)

Data endianness at reset.

CFGIE

SLCR configurable (default 0)

Instruction fetch endianness.

TEINIT

SLCR configurable (default 0)

Arm or fetch at reset. 0 = Arm.

CFGNMFIm

SLCR configurable (default 0)

Non-maskable FIQ. 0 = maskable.

INITPPXm

0x1

AXI peripheral interface enabled at reset.

SLBTCMSBm

SLCR configurable (default 0)

B0TCM and B1TCM interleaving by addr[3].

INITRAMAm

0x0

Enable ATCM.

INITRAMBm

0x1

Enable BTCM.

ENTCM1IFm

0x1

Enable B1TCM interface.

LOCZRAMAm

0x1

When High indicates ATCM initial base address is zero.

PPXBASEm

Based on global address map

Base address of AXI peripheral interface. Must be size aligned.

PPXSIZEm

16 MB

Size of AXI peripheral interface.

PPVBASEm

Same as PPXBASEm

Base address of virtual-AXI peripheral interface.

PPVSIZEm

8 KB

Size of virtual-AXI peripheral interface.

GROUPID[3:0]

0x1

ID of the Cortex-R5F processor group.

DBGNOCLKSTOP

default (0)

Clock control when entering standby.

SLSPLIT

default (0)

Processor mode

SLCLAMP

default (1)

Output clamps for redundant processor.

TCM_COMB

default (1)

Combine TCMs of RPU0 and RPU1.

TCM_WAIT

default (0)

Insert wait states in TCM access.

TCM_CLK_CNTL

default (0)

TCM clock disable (all TCMs, both RPU processors).

GIC_AXPROT

default (0)

GIC access security setting. This bit is equivalent to AxPROT[1] on AXI bus.

Note:   For more information on Configuration Signals, see the ARM Cortex-R5F and Cortex-R5F Technical Reference Manual [Ref 47].