RPU Reset Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each of the Arm Cortex-R5F real-time processors can be independently reset. In lock-step, only the R5_0 needs to be reset to reset both Cortex-R5F processors. It can be triggered by errors or a software register write. The Cortex-R5F reset can be triggered (due to a lock-step error) to reset and restart the RPU. It needs to gracefully terminate the Cortex-R5F ingress/egress transactions before initiating reset of the corresponding Cortex-R5F processor. The following steps describe a special case RPU reset.

An error is asserted which requires a Cortex-R5F processor reset. This request is sent to the PMU as an interrupt.

Block the Cortex-R5F processor master interfaces with the help of the AIB.

If an AIB acknowledgment is not received, then the software should timeout and continue.

Block the Cortex-R5F processor slave interfaces with the help of the AIB.

If an AIB acknowledgment is not received, then the software should timeout and continue.

Unblock the Cortex-R5F processor master interfaces.

Assert the Cortex-R5F processor reset. Use the PMU global register.

Deassert the Cortex-R5F processor reset, which will trigger a Cortex-R5F processor reboot.

Unblock the Cortex-R5F processor slave interfaces.

Note:   While in lock-step mode the R5F’s will continue to run until either the PMU intervenes, the error itself disrupts the R5F's operation or the normal operation causes a halt. There is no provision within the RPU to specifically inhibit/alter operation of the R5F’s in response to a mismatch.