RTC Register List

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The RTC registers are mapped in a 4 KB space starting at 0xFFA6_0000. The description and offset address for each register is listed in Table 7-3.

Table 7-3:      RTC Register List

Register Name

Offset

Width

Type

System Reset Value

Description

SET_TIME_WRITE

0x000

32

Write only

0

Program the RTC with the current time.

SET_TIME_READ

0x004

32

Read only

0

Read the last setting done by SET_TIME_WRITE.

CALIB_WRITE

0x008

21

Write only

0

Store the value that is used to generate one second based on the oscillator period.

CALIB_READ

0x00C

21

Read only

0

Read back the calibration value that was programmed in the RTC.

CURRENT_TIME

0x010

32

Read only

0

32-bit timer value in seconds.

ALARM(1)

0x018

32

Read/Write

0

Program the alarm value for the RTC.

RTC_INT_STATUS(1)

0x020

2

Write to clear

0

Raw interrupt status.

RTC_INT_MASK

0x024

2

Read only

11 b

Interrupt mask applied to the status.

RTC_INT_EN

0x028

2

Write only

0

Write a 1 to enable an interrupt.

RTC_INT_DIS

0x02C

2

Write only

0

Write a 1 to disable an interrupt.

ADDR_ERROR

0x030

1

Write to clear

0

Register address decode error interrupt status.

ADDR_ERROR_
INT_MASK

0x034

1

Read only

1 b

Register address decode error interrupt mask.

ADDR_ERROR_
INT_EN

0x038

1

Write only

0

Write a 1 to enable address decode error interrupt.

ADDR_ERROR_
INT_DIS

0x03C

1

Write only

0

Write a 1 to disable address decode error interrupt.

CONTROL

0x040

32

Read/Write

0100_0000 h

Controls the battery enable, clock crystal enable, and APB address decode error.

SAFETY_CHK

0x050

32

Read/Write

0

Safety endpoint connectivity check register.

Notes:

1.Due to the sticky nature of the alarm interrupt status register, clearing the alarm interrupt status register can be done only after the second counter outruns the set alarm value.