RX Buffers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Received frames, optionally including FCS, are written to receive AXI buffers stored in memory. The start location for each receive AXI buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive-buffer queue pointer. The base address for the receive-buffer queue pointer is configured in software using the receive-buffer queue base address register.

The number of words in each buffer descriptor depends on the operating mode. Each buffer descriptor word is defined as 32 bits. The first two words (word 0 and word 1) are used for all buffer descriptor modes. In extended buffer descriptor modes (DMA configuration register bit 28 = 1), two buffer descriptor words are added for 64-bit addressing mode and two buffer descriptor words are added for timestamp capture. Therefore, there are either two, four, or six buffer descriptor words in each buffer descriptor entry depending on operating mode, and every buffer descriptor entry has the same number of words.

Every descriptor is 64-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is disabled.

Every descriptor is 128-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is disabled.

Every descriptor is 128-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is enabled.

Every descriptor is 192-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is enabled.

Table: RX Buffer Descriptor Entry includes details on the receive buffer descriptor list.

Each receive AXI buffer start location is a word address. The start of the first AXI buffer in a frame can be offset by up to three bytes depending on the value written to bits [14] and [15] of the network configuration register. If the start location of the AXI buffer is offset the available length of the first AXI buffer is reduced by the corresponding number of bytes.

Table 34-5:      RX Buffer Descriptor Entry

Bit

Function

Word 0

31:3

Address of beginning of buffer.

2

Address [2] of beginning of buffer, or in extended buffer descriptor mode (DMA configuration register [28] = 1), indicates a valid timestamp in the buffer descriptor entry.

1

Wrap: Marks the last descriptor in the receive buffer descriptor list.

0

Ownership: This bit must be zero for the controller to write data to the receive buffer. The controller sets this bit to 1 once the frame is written to memory. Software must clear this bit before the buffer can be used again.

Word 1

31

Global all ones broadcast address detected.

30

Multicast hash match.

29

Unicast hash match.

28

I/O address match.

27

Specific address register match found, bit [25] and [26] indicate the specific address register that caused the match.

26:25

Specific address register match. The encoded matches are listed.

00b: Specific address register 1 match

01b: Specific address register 2 match

10b: Specific address register 3 match

11b: Specific address register 4 match

If more than one specific address is matched, only one is indicated with priority 4 down to 1.

24

This bit indicates different information when the RX checksum offloading is enabled or disabled.

With RX checksum offloading disabled, bit [24] is cleared and the network configuration type ID register match is found. Bit [22] and bit [23] indicates which type ID register caused the match.

With RX checksum offloading enabled, bit [24] is set in the network configuration.

0b: The frame is not SNAP encoded and/or has a VLAN tag with the CFI bit set.

1b: The frame is SNAP encoded and has either no VLAN tag or a VLAN tag without the CFI bit set.

23:22

These bits indicate different information when the RX checksum offloading is enabled or disabled.

With RX checksum offloading disabled, bit [24] is cleared in the network configuration type ID register match. The encoded matches are listed.

00b: Type ID register 1 match

01b: Type ID register 2 match

10b: Type ID register 3 match

11b: Type ID register 4 match

If more than one type ID is matched, only one is indicated with priority 4 down to 1.

With RX checksum offloading enabled, bit [24] is set in the network configuration.

00b: Both the IP header checksum and the TCP/UDP checksum were not checked.

01b: The IP header checksum is checked and is correct. Both the TCP or UDP checksum were not checked.

10b: Both the IP header and TCP checksum were checked and were correct.

11b: Both the IP header and UDP checksum were checked and were correct.

21

VLAN tag detected: Type ID of 0x8100. For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100.

20

Priority tag detected: Type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit is set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier.

19:17

VLAN priority: Only valid if bit [21] is set.

16

Canonical format indicator (CFI) bit: Only valid if bit [21] is set.

15

End of frame: When set, the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame bit [14].

14

Start of frame: When set, the buffer contains the start of a frame. If both bits [15] and [14] are set, the buffer contains a whole frame.

13

This bit indicates different information when the ignore FCS mode is enabled or disabled.

This bit is zero if ignore FCS mode is disabled.

When ignore FCS mode is enabled, bit [26] is set in the network configuration register. The per-frame FCS status indicates the following.

0b: Frame had good FCS.

1b: Frame had bad FCS and if the ignore FCS mode is enabled, the frame is copied to memory.

12:0

These bits represent the length of the received frame that could include FCS if the FCS discard mode is enabled or disabled.

FCS discard mode disabled: Bit [17] is cleared in the network configuration register. The least significant 12 bits for length of frame include FCS.

FCS discard mode enabled: Bit [17] is set in the network configuration register. The least significant 12 bits for length of frame exclude FCS.

Table: RX Descriptor Words: 64-bit Addressing Mode identifies the added descriptor words used when the 64-bit addressing mode is enabled.

Table 34-6:      RX Descriptor Words: 64-bit Addressing Mode

Bit

Function

Word 2 (64-bit Addressing)

31:0

Upper 32-bit address of the data buffer.

Word 3 (64-bit Addressing)

31:0

Unused

Table: RX Descriptor Words: Descriptor Timestamp Capture Mode identifies the added descriptor words used when the descriptor timestamp capture mode is enabled.

Table 34-7:      RX Descriptor Words: Descriptor Timestamp Capture Mode

Bit

Function

Word 2 (32-bit Addressing) or Word 4 (64-bit Addressing)

31:30

Timestamp seconds [1:0]

29:0

Timestamp nanoseconds [29:0]

Word 3 (32-bit Addressing) or Word 5 (64-bit Addressing)

31:4

Unused

3:0

Timestamp seconds [5:2]

The start location of the receive-buffer descriptor list must be written with the receive-buffer queue base address before reception is enabled (receive enable in the network control register). Once reception is enabled, any writes to the receive-buffer queue base address register are ignored.

When read, it returns the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled.

If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered.

An internal counter represents the receive-buffer queue pointer and it is not visible through the CPU interface. The receive-buffer queue pointer increments by two words after using each buffer. It re-initializes to the receive-buffer queue base address when any descriptor has its wrap bit set.

As receive AXI buffers are used, the receive AXI buffer manager sets bit zero of the first word of the descriptor to logic one, to indicate that the AXI buffer was used.

Software should search through the used bits in the AXI buffer descriptors to determine how many frames are received by checking the start of frame and end of frame bits.

For low latency requirements, GEM supports receive partial store and forward in packet buffer mode. The rx watermark or cut-thru is user defined.

When the receive partial store and forward mode is activated, the receiver will only begin to forward the packet to the external AHB or AXI slave when enough packet data is stored in the packet buffer. The amount of packet data required to activate the forwarding process is programmable via watermark registers, which are located at the same address as the partial store and forward enable bits.

Enabling partial store and forward is useful to reduce latency, but there are performance implications. For example, the packet buffer DMA will start behaving in a similar way to the internal FIFO DMA mode when partial store and forward is enabled.

Note:   When partial store and forward is enabled, checksum offload is not supported.

Since the DMA is configured in the packet buffer partial store and forward mode, received frames are written out to the AHB/AXI buffers as soon as sufficient frame data exists in the packet buffer. Therefore, several full buffers are used before error conditions can be detected. If a receive error is detected, the receive buffer currently being written will be recovered, but the previous buffers will not be recovered. For example, when receiving frames with CRC errors or excessive length, it is possible that a frame fragment may be stored in a sequence of receive buffers. Software can detect these fragments by looking for the start-of-frame bit set in a buffer, following a buffer with no-end-of frame bit set.

A properly working 10/100/1000 Ethernet system does not have excessive length frames or frames greater than 128 bytes with CRC errors. When using a default value of 128 bytes for the receive buffer, it is rare to find a frame fragment in a receive AXI buffer, because collision fragments are less than 128 bytes long.

Only good received frames are written out of the DMA and no fragments exist in the AXI buffers due to MAC receiver errors. However, there is still the possibility of fragments due to DMA errors, for example, when a used bit is read on the second buffer of a multi-buffer frame.

If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive AXI buffer, then the buffer is already used and cannot be used again until the software has processed the frame and cleared bit zero. In this case, the buffer not available bit in the receive status register is set and an interrupt is triggered. The receive resource error statistics register is also incremented.

There is an option to automatically discard received frames when no AXI buffer resource is available. Bit [24] of the DMA configuration register controls this option. By default, the received frames are not automatically discarded. When this feature is off, the received packets remain stored in the packet buffer until an AXI buffer resource becomes available. This can lead to an eventual packet buffer overflow occurs when packets continue to be received because the [0, used] bit of the receive-buffer descriptor is still set.

After a used bit is read, the receive-buffer manager re-reads the location of the receive buffer descriptor every time a new packet is received.

When the DMA is configured in the packet buffer full store and forward mode, a receive overrun condition occurs when the receive packet buffer is full, or if an AMBA AXI error occurred.

For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer.

A write to bit [18] of the network control register forces a flush of the packet from the receive packet buffer. This only occurs when the RX DMA is not currently writing packet data out to the AXI (that is, it is in an IDLE state). If the RX DMA is active, a write to this bit is ignored.