Received frames, optionally including FCS, are written to receive AXI buffers stored in memory. The start location for each receive AXI buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive-buffer queue pointer. The base address for the receive-buffer queue pointer is configured in software using the receive-buffer queue base address register.
The number of words in each buffer descriptor depends on the operating mode. Each buffer descriptor word is defined as 32 bits. The first two words (word 0 and word 1) are used for all buffer descriptor modes. In extended buffer descriptor modes (DMA configuration register bit 28 = 1), two buffer descriptor words are added for 64-bit addressing mode and two buffer descriptor words are added for timestamp capture. Therefore, there are either two, four, or six buffer descriptor words in each buffer descriptor entry depending on operating mode, and every buffer descriptor entry has the same number of words.
•Every descriptor is 64-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is disabled.
•Every descriptor is 128-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is disabled.
•Every descriptor is 128-bits wide when 64-bit addressing is disabled and the descriptor timestamp capture mode is enabled.
•Every descriptor is 192-bits wide when 64-bit addressing is enabled and the descriptor timestamp capture mode is enabled.
Table: RX Buffer Descriptor Entry includes details on the receive buffer descriptor list.
Each receive AXI buffer start location is a word address. The start of the first AXI buffer in a frame can be offset by up to three bytes depending on the value written to bits  and  of the network configuration register. If the start location of the AXI buffer is offset the available length of the first AXI buffer is reduced by the corresponding number of bytes.
Table: RX Descriptor Words: 64-bit Addressing Mode identifies the added descriptor words used when the 64-bit addressing mode is enabled.
Word 2 (64-bit Addressing)
Upper 32-bit address of the data buffer.
Word 3 (64-bit Addressing)
Table: RX Descriptor Words: Descriptor Timestamp Capture Mode identifies the added descriptor words used when the descriptor timestamp capture mode is enabled.
The start location of the receive-buffer descriptor list must be written with the receive-buffer queue base address before reception is enabled (receive enable in the network control register). Once reception is enabled, any writes to the receive-buffer queue base address register are ignored.
When read, it returns the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered.
An internal counter represents the receive-buffer queue pointer and it is not visible through the CPU interface. The receive-buffer queue pointer increments by two words after using each buffer. It re-initializes to the receive-buffer queue base address when any descriptor has its wrap bit set.
As receive AXI buffers are used, the receive AXI buffer manager sets bit zero of the first word of the descriptor to logic one, to indicate that the AXI buffer was used.
Software should search through the used bits in the AXI buffer descriptors to determine how many frames are received by checking the start of frame and end of frame bits.
For low latency requirements, GEM supports receive partial store and forward in packet buffer mode. The rx watermark or cut-thru is user defined.
When the receive partial store and forward mode is activated, the receiver will only begin to forward the packet to the external AHB or AXI slave when enough packet data is stored in the packet buffer. The amount of packet data required to activate the forwarding process is programmable via watermark registers, which are located at the same address as the partial store and forward enable bits.
Enabling partial store and forward is useful to reduce latency, but there are performance implications. For example, the packet buffer DMA will start behaving in a similar way to the internal FIFO DMA mode when partial store and forward is enabled.
Note: When partial store and forward is enabled, checksum offload is not supported.
Since the DMA is configured in the packet buffer partial store and forward mode, received frames are written out to the AHB/AXI buffers as soon as sufficient frame data exists in the packet buffer. Therefore, several full buffers are used before error conditions can be detected. If a receive error is detected, the receive buffer currently being written will be recovered, but the previous buffers will not be recovered. For example, when receiving frames with CRC errors or excessive length, it is possible that a frame fragment may be stored in a sequence of receive buffers. Software can detect these fragments by looking for the start-of-frame bit set in a buffer, following a buffer with no-end-of frame bit set.
A properly working 10/100/1000 Ethernet system does not have excessive length frames or frames greater than 128 bytes with CRC errors. When using a default value of 128 bytes for the receive buffer, it is rare to find a frame fragment in a receive AXI buffer, because collision fragments are less than 128 bytes long.
Only good received frames are written out of the DMA and no fragments exist in the AXI buffers due to MAC receiver errors. However, there is still the possibility of fragments due to DMA errors, for example, when a used bit is read on the second buffer of a multi-buffer frame.
If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive AXI buffer, then the buffer is already used and cannot be used again until the software has processed the frame and cleared bit zero. In this case, the buffer not available bit in the receive status register is set and an interrupt is triggered. The receive resource error statistics register is also incremented.
There is an option to automatically discard received frames when no AXI buffer resource is available. Bit  of the DMA configuration register controls this option. By default, the received frames are not automatically discarded. When this feature is off, the received packets remain stored in the packet buffer until an AXI buffer resource becomes available. This can lead to an eventual packet buffer overflow occurs when packets continue to be received because the [0, used] bit of the receive-buffer descriptor is still set.
After a used bit is read, the receive-buffer manager re-reads the location of the receive buffer descriptor every time a new packet is received.
When the DMA is configured in the packet buffer full store and forward mode, a receive overrun condition occurs when the receive packet buffer is full, or if an AMBA AXI error occurred.
For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer.
A write to bit  of the network control register forces a flush of the packet from the receive packet buffer. This only occurs when the RX DMA is not currently writing packet data out to the AXI (that is, it is in an IDLE state). If the RX DMA is active, a write to this bit is ignored.