RX Clock Delay Unit

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The RX clock delay unit is used to support receive clock tuning to center align the receive data to the receive clock. There are two modes for delaying the receive clock. The first one is the automatic tuning of the receive clock when operating in SDR104 modes in SD 3.0 or eMMC 4.51 in SDR50 modes. The second one is under manual controls to offset for post-silicon board delays. The manual control is implemented for high-speed mode and SDR25/SDR50/DDR50 modes using the corectrl_itapdlysel and corectrl_itapdlyen signals.

The maximum number of tap delays (phases of the clock) is 180, but the useful number of tap delays is greatly reduced as the clock frequency goes up. A typical design uses four to eight tap delay selections.

The preferred method uses the looped back SD_CLK (rxclk_in) to generate multiple phases of the clock. In the case of a DLL-based approach, this looped back clock is not ideal because the clock itself can dynamically be stopped by the host controller to pause the data reception from the SD/eMMC card. Because the DLL takes longer times to lock the clock, a continuous clock is needed. Because the SD_CLK is a gated version of the internal sd_clk, Xilinx recommends using the sd_clk as the input to the RXCLK delay unit.