RX Packet Buffer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The receive packet buffer stores frames from the MAC receiver along with their status and statistics.

Frames with errors are flushed from the packet buffer memory, good frames are pushed onto the DMA AXI interface.

The receiver packet buffer monitors the FIFO writes from the MAC receiver and translates the FIFO pushes into packet buffer writes. At the end of the received frame, the status and statistics are buffered to use the information when the frame is read out. When programmed in full store and forward mode, if the frame has an error, the frame data is immediately flushed from the packet buffer memory allowing subsequent frames to use the newly opened space. The status and statistics for bad frames are still used to update the controller's registers.

To accommodate the status and statistics associated with each frame, three words per packet are reserved at the end of the packet data. When a packet is bad and is dropped, the status and statistics are the only information held on that packet.

The receiver packet buffer can detect a full condition and an overflow condition can also be detected. If this occurs, subsequent packets are dropped and an RX overflow interrupt is raised.

The DMA only begins packet fetches when the status and statistics for a frame are available. If the frame has a bad status due to a frame error, the status and statistics are passed onto the controller's registers. If the frame has a good status, the information is used to read the frame from the packet buffer memory and burst onto the AXI using the DMA buffer management protocol. After the last frame data is transferred to the FIFO, the status and statistics are updated to the controller's registers.