RX and TX Error Counters

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When an RX or TX error occurs, the associated error counters in the protocol engine (see Protocol Engine) are incremented. The two error counters are 8 bits wide and are read using the read-only can.ECR register, bit fields [REC] and [TEC]. The RX and TX counters are reset when any the these situations occur.

After a 1 is written to can.SRR[SRST] field = 1. This bit write is self-clearing.

Anytime can.SRR[CEN] = 0 (configuration mode).

When the controller enters the bus-off state.