RX/TX Bit Timing Logic

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The primary functions of the bit timing logic (BTL) module include the following.

Generate the RX sampling clock for the bitstream processor (BSP).

Synchronize the CAN controller to CAN traffic on the bus.

Sample the bus and extracting the data stream from the bus during reception.

Insert the transmit bitstream onto the bus during transmission.

The nominal length of the bit time clock period is based on the CAN_REF_CLK clock frequency, the baud rate generator divider (can.BRPR register), and the segment lengths (can.BTR register).

The bit timing logic module manages the re-synchronization function for CAN using the sync width parameter in the can.BTR[SJW] bit field. The CAN bit timing is shown in This Figure.

The sync segment count always equals one time quanta period. The TS 1 and TS 2 period counts are programmable using the can.BTR[TS1, TS2] bit fields. These registers are written when the controller is in configuration mode. The width of the propagation segment (PROP_SEG) must be less than the actual propagation delay.

Figure 20-6:      CAN Bit Time

X-Ref Target - Figure 20-6

X15376-bit-timing.jpg