Read Address Channel

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The AXI read address channel has the following features.

The read transaction can be of any length up to 16.

The burst types supported are incremental and wrapping. Fixed burst is not supported.

The burst start address can be unaligned to the AXI data width boundaries.

The size of the burst can be less than the full width of the AXI data bus (also known as sub-sized transfers).

All read requests are stored in read-address queue (RAQ). Generation of new read requests are based on alignment (derived from AXI address and size), burst lengths (derived from AXI length and memory burst length), and burst type (derived from AXI incremental or wrapping). Each AXI burst is divided into packets of length equal to the memory burst length (BL4, BL8, or BL16). In case of an unaligned burst, the first read request is unaligned and the remaining read requests are aligned. In general, realignment to a memory burst boundary potentially causes some data beats to be discarded (affecting bandwidth) and potentially introduces additional latency on the read data and response channel. The XPI handles the generation of the token that is used by the DDRC for identifying the read command and corresponding data.