The read bit deskew algorithm is performed in parallel for all byte lanes and requires write and read access to memory. The goal of the PHY read bit deskew algorithm is to align a 0-to-1 transition on each of the data bits in the read path. An initial pattern is written into memory, read back, and then evaluated. Then per-bit delay lines are used to align all the data bits to each other. After deskewing, another read is executed to confirm data integrity.
Read bit deskew completion is signaled by the PGSR0.RDDONE bit. The high-level error flag is PGSR0.RDERR. Additional debugging information is listed in Table: DATX8 General Status Register 2 (DXnGSR2) and Table: Read Bit Deskew Error Indications.
The results of read bit deskew can be viewed in the DXnBDLR3, DXnBDLR4, and DXnBDLR5 registers, as listed in Table: Read Bit Deskew Results Registers.