Read Bit Deskew

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The read bit deskew algorithm is performed in parallel for all byte lanes and requires write and read access to memory. The goal of the PHY read bit deskew algorithm is to align a 0-to-1 transition on each of the data bits in the read path. An initial pattern is written into memory, read back, and then evaluated. Then per-bit delay lines are used to align all the data bits to each other. After deskewing, another read is executed to confirm data integrity.

Read bit deskew completion is signaled by the PGSR0.RDDONE bit. The high-level error flag is PGSR0.RDERR. Additional debugging information is listed in Table: DATX8 General Status Register 2 (DXnGSR2) and Table: Read Bit Deskew Error Indications.

Table 17-18:      DATX8 General Status Register 2 (DXnGSR2)

Register

Bits

Name

Description

Address

DX0GSR2

[0]

RDERR

Read bit deskew error: if set, indicates that the DATX8 has encountered an error during execution of the read bit deskew training of byte 0.

0xFD0807E8

DX1GSR2

[0]

RDERR

Same as above, for byte 1.

0xFD0808E8

DX2GSR2

[0]

RDERR

Same as above, for byte 2.

0xFD0809E8

DX3GSR2

[0]

RDERR

Same as above, for byte 3.

0xFD080AE8

DX4GSR2

[0]

RDERR

Same as above, for byte 4.

0xFD080BE8

DX5GSR2

[0]

RDERR

Same as above, for byte 5.

0xFD080CE8

DX6GSR2

[0]

RDERR

Same as above, for byte 6.

0xFD080DE8

DX7GSR2

[0]

RDERR

Same as above, for byte 7.

0xFD080EE8

DX8GSR2

[0]

RDERR

Same as above, for byte 8.

0xFD080FE8

DX0GSR2

[1]

RDWN

Read bit deskew warning: if set, indicates that the DATX8 has encountered a warning during execution of the read bit deskew training of byte 0.

0xFD0807E8

DX1GSR2

[1]

RDWN

Same as above, for byte 1.

0xFD0808E8

DX2GSR2

[1]

RDWN

Same as above, for byte 2.

0xFD0809E8

DX3GSR2

[1]

RDWN

Same as above, for byte 3.

0xFD080AE8

DX4GSR2

[1]

RDWN

Same as above, for byte 4.

0xFD080BE8

DX5GSR2

[1]

RDWN

Same as above, for byte 5.

0xFD080CE8

DX6GSR2

[1]

RDWN

Same as above, for byte 6.

0xFD080DE8

DX7GSR2

[1]

RDWN

Same as above, for byte 7.

0xFD080EE8

DX8GSR2

[1]

RDWN

Same as above, for byte 8.

0xFD080FE8

DX0GSR2

[11:8]

ESTAT

Error status: if an error occurred for byte 0 as indicated by RDERR, the error status code can provide additional information regarding when the error occurred during the algorithm execution.

0xFD0807E8

DX1GSR2

[11:8]

ESTAT

Same as above, for byte 1.

0xFD0808E8

DX2GSR2

[11:8]

ESTAT

Same as above, for byte 2.

0xFD0809E8

DX3GSR2

[11:8]

ESTAT

Same as above, for byte 3.

0xFD080AE8

DX4GSR2

[11:8]

ESTAT

Same as above, for byte 4.

0xFD080BE8

DX5GSR2

[11:8]

ESTAT

Same as above, for byte 5.

0xFD080CE8

DX6GSR2

[11:8]

ESTAT

Same as above, for byte 6.

0xFD080DE8

DX7GSR2

[11:8]

ESTAT

Same as above, for byte 7.

0xFD080EE8

DX8GSR2

[11:8]

ESTAT

Same as above, for byte 8.

0xFD080FE8

Table 17-19:      Read Bit Deskew Error Indications

PGSR0.RDERR

DXnGSR2.RDERR

DXnGSR2.ESTAT

PGSR0.

RDDONE

Error Condition

1

1

0000

1

Initial read data is skewed by more than three beats of data prior to any deskew.

1

1

0001

1

Read DQS/DQS# is too early relative to data, and during deskew, DQS/DQS# LCDL is at maximum value and any read DQ BDL is at minimum value.

1

1

0010

1

While searching for left edge of read data eye, DQS/DQS# LCDL is at the minimum value and any read DQ BDL is at the maximum value.

1

1

0101

1

While searching for right edge of read data eye, DQS/DQS# LCDL is at the maximum value and any read DQ BDL is at the minimum value.

1

1

0111

1

Read data miscompare after read bit deskew.

The results of read bit deskew can be viewed in the DXnBDLR3, DXnBDLR4, and DXnBDLR5 registers, as listed in Table: Read Bit Deskew Results Registers.

Table 17-20:      Read Bit Deskew Results Registers

Register

Bits

Name

Description

Address

DXnBDLR3

[5:0]

DQ0RBD

DQ0 read bit delay: delay select for the BDL on DQ0 read path.

FD080750, FD080850, FD080950, FD080A50, FD080B50, FD080C50, FD080D50, FD080E50, FD080F50

DXnBDLR3

[13:8]

DQ1RBD

DQ1 read bit delay: delay select for the BDL on DQ1 read path.

FD080750, FD080850, FD080950, FD080A50, FD080B50, FD080C50, FD080D50, FD080E50, FD080F50

DXnBDLR3

[21:16]

DQ2RBD

DQ2 read bit delay: delay select for the BDL on DQ2 read path.

FD080750, FD080850, FD080950, FD080A50, FD080B50, FD080C50, FD080D50, FD080E50, FD080F50

DXnBDLR3

[29:24]

DQ3RBD

DQ3 read bit delay: delay select for the BDL on DQ3 read path.

FD080750, FD080850, FD080950, FD080A50, FD080B50, FD080C50, FD080D50, FD080E50, FD080F50

DXnBDLR4

[5:0]

DQ4RBD

DQ4 read bit delay: delay select for the BDL on DQ4 read path.

FD080754, FD080854, FD080954, FD080A54, FD080B54, FD080C54, FD080D54, FD080E54, FD080F54

DXnBDLR4

[13:8]

DQ5RBD

DQ5 read bit delay: delay select for the BDL on DQ5 read path.

FD080754, FD080854, FD080954, FD080A54, FD080B54, FD080C54, FD080D54, FD080E54, FD080F54

DXnBDLR4

[21:16]

DQ6RBD

DQ6 read bit delay: delay select for the BDL on DQ6 read path.

FD080754, FD080854, FD080954, FD080A54, FD080B54, FD080C54, FD080D54, FD080E54, FD080F54

DXnBDLR4

[29:24]

DQ7RBD

DQ7 read bit delay: delay select for the BDL on DQ7 read path.

FD080754, FD080854, FD080954, FD080A54, FD080B54, FD080C54, FD080D54, FD080E54, FD080F54

DXnBDLR5

[5:0]

DMRBD

DM read bit delay: delay select for the BDL on DM read path.

FD080758, FD080858, FD080958, FD080A58, FD080B58, FD080C58, FD080D58, FD080E58, FD080F58